1. Field of the Invention
The present invention relates to a semiconductor package, and more particularly, to a semiconductor package using a chip-embedded interposer substrate.
2. Description of the Related Art
With the advent of the digital information age, multimedia products, electrical home appliances, personal digital products and the like have been rapidly developed. These products generally require characteristics of small size, high performance, multiple functions, high speed, large capacity, low price, and the like. Accordingly, a stacked package or system in package, in which a plurality of chips are stacked in parallel or vertically on top of one another in a single semiconductor package, has been developed.
A stacked package or system in package includes a plurality of chips assembled in a single package, and has advantages in that electrical performance can be enhanced, the size of the package can be reduced, and fabrication costs can be reduced. However, since the pitch of chip pads is small in stacked packages or system in packages, connection between chip pads and interconnection pads of an interconnection substrate is difficult.
To solve such a problem, a multi-layered interconnection substrate or additional interposer chip for connection between chip pads and interconnection pads of an interconnection substrate is used in stacked packages or system in package. That is, in a conventional stacked package or system in package, a redistribution layer is formed in a multi-layered interconnection substrate or additional interposer chip, and chip pads are then connected to interconnection pads of an interconnection substrate using the redistribution layer.
However, since redistribution is performed using the multi-layered interconnection substrate or additional interposer chip in the conventional stacked package or system in package, packaging cost is increased, and a packaging process for connection between chip pads and interconnection pads of an interconnection substrate is very complicated.